Switching network



m 4, 1967 G. W.IBOOTH ETAL 3,312,941

SWITCHING NETWORK Original Filed Nov. 1, 1955 2 Sheets-Sheet 1 IN V ENTORS GRANT W. BunTH if ATTORNEY United States Patent Ofiice 3,312,941SWITCHING NETWORK Grant W. Booth, Framingham, Mass, and Charles S.

Warren, Riverside, N.J., assignors to Radio Corporation of America, acorporation of Delaware Continuation of application Ser. No. 544,280,Nov. 1, 1955. This application June 24, 1963, Ser. No. 293,922 6 Claims.((31,340-166) This is a continuation of application Ser. No. 544,280,filed Nov. 1, 1955.

This invention relates to switching networks, and particularly toswitching networks using transistors.

Switching networks are used, for example, in commutating anddistributing applications for selecting one out of many signal lines forreceiving or transmitting an electric signal. .Known types of suchdevices include arrays of bistable elements wherein any one element andits connected signal line are selected by applying to the array inputs acombination of address signals corresponding to that element. It isoften desirable to provide a switching network of this type that offersa relatively low electrical resistance path from a common source to thesignal line of the array element. It is further desirable to provide aswitching network that, in addition to performing a selection function,also operates to amplify the address signals, thereby permitting the useof signals in controlling the array of lower power level than otherwisewould be possible.

It is an object of the present invention to provide an improvedswitching network of the last-mentioned type which operates to select adesired signal line and which operates to amplify signals used inselecting the desired line.

Another object of the present invention is to provide i an improvedswitching network using transistors of different conductivity typeswhich provides a relatively low re sistance path between a common sourceand any selected one of a plurality of signal lines.

Still another object of the present invention is to provide an improvedtransistor network using fewer transistors than networks of a similartype heretofore known.

According to the invention, a switching network has respective ones of aplurality of signal lines connected to separate ones of an array oftransistors, and has a desired one of the sign-a1 lines selected byproviding separate bias means for the base and emitter electrodes of thearrayed transistors so arranged that a selected one of the arrayedtransistors maybe placed in conductive condition.

An array of transistors may be arranged, for example, in rows andcolumns; a first group of transistors of the same conductivity type asthe arrayed transistors may control selection of the array columns, anda se-cond group of transistors of conductivity type opposite that of thearrayed transistors may control the selection of the array rows. Theselected signal line is the one connected to the one transistor of thearray located at the intersection of a selected row and column. All thesignal paths, including the signal lines, may be normally open. When asignal line is selected, a signal path is completed from a commonreference source through the collect-or-emitter path of one or moretransistors of the first or second group and the collector-emitter pathof the selected array transistor to the selected signal line. Thissignal path is one of a relatively low resistance, say in the order of afew hundred ohms; the non-selected signal lines provide relatively highresist-ance paths, say in the order of a megohm or more, according tothe particular circuit configuration. The transistors of the first andsecond groups and the selected array transistor each furnish a stageofamplification. Accordingly, a relatively high cur- 3,312,941 PatentedApr. 4, 1967 rent supplied from a source to the signal lines can becontrolled by relatively low current signals applied to the first andsecond transistor groups.

The invention will be further explained in connection with the followingdescription and the accompanying drawing wherein:

FIG. 1 is a schematic diagram of a switching network according to theinvention;

FIG. 2 is a schematic diagram of a memory system utilizing first andsecond switching matrices according to the invention;

FIGS. 3 and 4 are schematic diagrams of suitable circuits for applyingbipolarity current pulses to the memory system of FIG. 2 under thecontrol of the selection matrices, according to the invention; and

FIG. 5 is aschematic diagram of one system for commutating time-varyinginput signals to a selected output channel. P 7

Referring to FIG. 1, a switching network 10 has a plurality, for examplesixteen, of signal lines '12. The signal lines 12 are connectedrespectively to the collector electrodes 18 of different ones of a 4x 4array of transistors 16. The transistors 16 are all of one conductivitytype; for example, the NPN type. Each has, in addition to the collectorelectrode 18, a base electrode 20 and an emitter electrode 22. The arraytransistors 16 may be arranged, for example, in four columns 24-27 andfour rows 32-35. The four columns 24-27 are selected, one at a tim-e,under the control of a first group of six transistors -45 arranged, forexample, in a pyramid array. Each of the transistors 40-45 is of theconductivity type NPN, and each has a base electrode 50, an emitterelectrode 52, and a collector electrode 54. The collector electrodes 54of the upper four transistors 40-43 of the first group are respectivelyconnected serially through four current-limiting resistors 58 to all theemitter electrodes 22 of the respective four columns 24-27 of thearrayed transistors 16. The upper four transistors 40-43 of the pyramidare controlled in pairs by. the lower two transistors 44 and 45 thereofby connecting the collector electrode 54 of the lower transistor 44 tothe emitter electrodes 52 of the transistors40 and 41, and by connectingthe collector electrode 54 of the lowerv transistor 45 to the emitterelectrodes 52 of the transistors 42 and 43. The emitter electrodes 52 ofthe transistors 44 and 45 areconnected to the negative'terminal 56 of avoltage source E2 which has its positive terminal 57 connected to acommon reference point, indicated in the drawing as the conventionalground symbol.

The four rows 32-35 of the array transistors are selected, under thecontrol of two different ones of a second group of six transistors60-65, also arranged in a pyramid array. Each of the transistors 60-65is of the PNP conductivity type and each has a base electrode 67, anemitter electrode 68, and a collector electrode 69. The collectorelectrodes 69 of the four transistors 60-63 of the second group areconnected respectively to all the base electrodes 18 of the separaterows 32-35 of the arrayed transistors 16. The four transistors 60-63 ofthe second group are controlled in pairs by the other two transistors 64and 65 of the second group by connecting the collector electrode 69 ofthe transistor 64 to the emitter electrodes 68 of the first pair 60 and61, and the collector electrode 69 of the transistor 65 to the emitterelectrodes 68 of the other pair 62 and 63. The emitter electrodes 68 ofthe two transistors 64 and 65 are connected to the positive terminal 70of a bias source E1 which has its negative terminal 71 connected to thecommon ground. The collectors 69 of the transistors 60-63 are connectedrespectively in series with separate ones of four collector resistors75-78 to the negative terminal 79 of a section.

ond bias source E3 which has its positive terminal 8%) connected to thecommon ground. Each of the base elec trodes 20 of the four rows 32-35 ofarrayed transistors 16 are connected to one terminal 81 of the separatecollector resistors 75-78. Accordingly, the source E3 normally reversebiases the transistors 16 of the 4 x 4 coordinate array.

; An address register 82 is used for selecting a desired signal line 12in accordance with the binary digits 2-2 of a four-position binary code.The four binary digits 2-2 are sufiicient for selecting any one of thesixteen signal lines 12 in the exemplary embodiment. The addressregister 82 may be any known type register; for example, a flipflopregister. Each of the flip-flops of the address register 102 has a set(S) and a reset (R) input and corresponding 1 and outputs. When afiip-fiop is in a set condition, a relatively high output signal isfurnished on its 1 output and when it is in a reset condition, arelatively low output signal is furnished on its 1 output. When aflip-flop is in a reset condition, a relatively high signal is furnishedon its 0 output, and when it is in a set condition, a relatively lowlevel signal is furnished on its 0 output. A pulse may be applied on acommon reset line 84 for resetting the address register flip-flopsduring operation. The 2-2 fiip-fiops of the address register 82 may beconnected to the common ground.

The first two binary digits 22 are used for selecting a desired columnof the arrayed transistors 16. Each of the transistors 40-45 has aseparate bias resistor 85 connected to its base electrode 50. The O and1 outputs of the 2 flip-flop of the address register 82 are connectedrespectively to the bias resistors 85 of the transistors 44 and 45. The0 output of the 2 address register flipfiop is connected to the biasresistors 85 of the transistors 40 and 42, and the 1 output of the 2flip flop is connected to the bias resistors 85 of the transistors 41and 43. The other two binary digits 2 -2 are used in selecting a desiredone of the rows 32-35 of the array transistors 16. .Each of thetransistors 60-65 of the second group has a separate bias resistor 86.The l and the 0 outputs of v the 2 fiip-fi-op are connected,respectively, to the bias resistors 86 of the transistors 64 and 65. The1 output of the 2 flip-flop is connected to the bias resistors 86 of thetransistors 60 and 62, and the 0 output of the 2 flip-flop is connectedto the bias resistors 86 of the tran sisters 61 and 63 of the secondgroup. i

In operation, the combination of binary digits 2-2 corresponding to theaddress of the selected array transistor 16 which is to be connected tothe desired signal line 12, is set into the address register 82. Theoutputs of the addressregister 82 then operate to bias this one arraytransistor 16 to a forward conduction condition. For example, assumethat it is desired'to select the top signal line 12' connected to thefirst row and column transistor 16 whose binary address is 0000. Forconvenience of description, the top signal line 12 is designated 12 andthe first row and column transistor is designated 16. Accordingly, eachof the flip-flops 2 -2 of the address register 82 is placed in a resetcondition by a pulse applied to the common reset line 84, thereby makingthe .0 output voltage of the 2 -2 flip-flops high relative to their 1output voltages.

The high-level 0 outputs of the 2-2 flip-flop respectively apply aforward bias on the transistors 40 and 44 of the first group, placingeach in a conductive condition. The low-level 1 outputs of the 2 -2flip-flops respectively apply a forward bias on the transistors 64 and60 of the second group, placing each in a conductive condi- Accordingly,the base electrodes 20 of the first row 32 of transistors 16, and theemitter electrodes 22 of the 4' paths of transistors and 44, and thesource E2. Therefore, the transistor 16' has a forward bias and isplaced in a conductive condition. Each of the other array transis'tors16 in the rows 33-35 has a reverse bias due to the negative potential -Eapplied to their base electrodes 20 via the collector resistors 76-78connected in the respective rows 33-35 of array transistors 16. Thethree remaining array transistors 16 of the first row 32 remain cut 011due to the reverse bias placed on the transistors 41 and 43 and thetransistor 45 by the low-level output of the 1 side of the flip-fiops 2and 2 respectively.

The 0 output of the 2 flip-flop also biases the transistor 42 of thefirst group 40-45 to a conductive condition. However, the signal paththrough this transistor remains open due to the reverse bias on thetransistor 45. Similarly, the "1 output of the 2 flip-flop biases thetranfirst column 24 of transistors16 assume a positive potential 7approximately equal to the value of +E This positive potential resultswhen current flows through the emitterto-base diode of transistor 16'and thence through the path which includes resistor 58, theemitter-to-collector sister 62 of the second group 60-65 to a conductivecondition, but current flow is prevented due to the reverse bias placedon the transistor 65.

Accordingly, the signal path from the desired signal line 12' iscompleted via the collector-to-emitter path of the selected arraytransistor 16', the current-limiting resistor 58 of the first column 24,and the collector-to-emitter paths of the transistors 40 and 44 of thefirst group, and then through the source E2 to the common ground. Theresistance of this path may be, for example, two hundred ohms and, inpractice, is determined by the value of the current-limiting resist-or58. Each of the other signal paths, including a signal line 12, remainsin an open condition and each has a resistance, for example, of a megohmor more, because the resistance of any open pat-h is determined by thecollector-to-emitter resistance of one or more reversed-biasedtransistors.

Note that the transistors 64 and 60 of the second group respectivelyamplify the 2 and 2 flip-fiop currents applied to their base electrodes67, and that the selected array transistor 16 also amplifies the currentapplied to its base electrode 20. Accordingly, in the exemplaryemb-odiment, the 2 and 2 flip-flop currents used in controlling theselection of the signal line 12 receive two stages of currentamplification. Similarly, the transistors 40 and 44 of the first groupeach operate to amplifycurrents applied to their base electrodes by the2 and 2 flipflops. Therefore, the flip-flop currents required to controlany given current flowing in a signal line 12 may be substantiallyreduced below that which would be required without amplification. Aneven increased reduction of the flip-flop currents required is obtainedin larger array using a larger number of transistors in the first andsecond i groups.

Any other one of the signal lines 12 can be selected in like manner bysetting the address of the array transistor 16 of that line into theaddress register 82. The 2 -2 and the reset inputs of the addressregister 82 may be controlled by any suitable means, for example, adigital computer.

The arrayed transistors 16, the first group of transistors 40-45, andthe second group of transistors -65, respectively, can be of theopposite conductivity type from those described in FIG. Thus, the arraytransistors 16 may be the PNP type; the first group 40-45 of transistorsthe PNP type, and the second group 60-65 of transistors the NPN type.The bias sources E1, E2 and E3 are then changed in appropriate fashionto accommodate the dilferent types of transistors. In such case the 1and 0 outputs of the address register 82 are reversed; otherwise, thearrangement and the operation of the switching network 10 is similar tothat just described. The array transistors 16 of a switching network maybe selected by using other selecting means in place of the first andsecond groups of transistors. For example, either one or both of thefirst and second group of transistors could be replaced by crystal diodematrices each having two binary inputs and four corresponding outputs.The respective outputs of the diode matrices then would be connected tothe rows or columns of the arrayed transistors 16.

In the exemplary embodiment, one of the signal lines 12 is alwaysselected because all sixteen combinations of the binary digits 2 -2 areused. If desired, the array transistor 16, corresponding to the resetcondition of the address register 82 may beomitted, thereby causing anyone of the remaining signal lines 12 to be selected only when itscorresponding addressis set into the address register 82. Other arraysof transistors 16-than a square array may be used, for example,arectangular array, a hexagonal array, or a Christmas-tree array may beemployed.

A plurality of switching networks, according to the invention, may beemployed for operating a known coincident current, magnetic core memory.For example, the memory system 90 of FIG. 2 includes a 16 x 16 matrix 92of magnetic memory cores arranged in sixteen rows and sixteen columns.Separate ones of the row coils 94 are linked to the memory cores in theseparate rows of the memory 92, and separate ones of the column coils 96are linked to the memory cores of the separate columns in the memory 92.A row switch 98 and a col umn switch 100 are used in applying currentrespectively to the one row coil 94 and the one column coil 96 whichintersect in any desired one of the memory cores of the memory 92.Details of suitable row and column switches 98 and 100 are describedhereinafter in connection with FIGS. 3 and 4. Each of the row and columnswitches 98 and 100 has sixteen separate current switches, and eachcurrent switch has a read winding and a write winding. Separate ones ofrow current switches are coupled to the separate row lines 94, andseparate ones of the column current switches are coupled to the separatecolumn lines 96. The sixteen inputs of the row switch 98 are suppliedvia a first transistor matrix and each of the sixteen inputs to thecolumn switch 100 is supplied via a second transistor matrix 10". Thematrices 10' and 10" are each similar to the switching network 10 ofFIG. 1. An address register 102 has eight binary outputs 2 -2 The firstfour binary inputs 2- 2 of the address register 102 are applied to thefirst and second groups of transistors in the first selection matrix10', in the manner described, for the four binary digits 2 and 2 of FIG.1, and the 2 --2 outputs of the addressregister 102 applied to thesecond selection matrix 10" in a similar manner. The eight set S inputsand the common reset input (R) of the address register 102 may befurnished under the control of any suitable means, for example, adigital computer. A pair of read drivers and a pair of write drivers areused to apply current pulses coincident in time to the row and columnswitches 98 and 100. One read driver of the pair is connected to all thesixteen read windings of the row switch 98, and the other read driver ofthe pair is connected to all the sixteen read windings of the columnswitch 100. One of the pair of write drivers is connected to all'thesixteen write windings of the row switch 98, and the other write driverof the pair is connected to all the sixteen write windings of the columnswitch 100. The read and write drivers may be, for example, knownvacuum-type circuits which operate to apply a pulse of constant currentfor its duration to the read and write windings of the row and columnswitches 98 and 100.

FIGURE 3 is a schematic diagram of one suitable form of current-switch106 for applying read-write pulses to the selected memory lines. Each ofthe sixteen current switches in the row and column switches98 and 100may be similar to that of FIG. 3. switch 106 includes a pulsetransformer 107 having as primary windings a read winding. 108 and awrite winding 109. The secondary winding 110 is connected to one of the,row or column coils 94 or 96 of the memory matrix 92 (FIG. 2). The twoprimary windings 108 and 1.09 are oppositely polarized so that the samepolarity current pulses applied to the primary windings induce oppositepolarity. currents in the connected memory line.

The current and 114.

One terminal of each of transformer 107 windings 108 has a dot placedadjacent thereto to indicate the sense of linkage in the conventionaltransformer manner. Two transistors 112 and 114 are used to controlcurrent flow in the primary windings 108 and 109 of the transformer 107.The collector electrode 116 of the transistor 112 is connected totheunmarked terminal of the first primary winding 108, and the collectorelectrode 116 of the transistor 114 is connected to the marked terminalof the other primary winding 109. The emitter electrodes 118 of thetransistors 112 and 114 are each connected to the positive terminal of abias source E4 which has its negative terminal 117 connected to thecommon ground. Each of the transistors 112 and 114 is normally cut-off.Separate base resistors 120 are connected to the base electrodes 122 ofthe transistors112 One of the signal lines 12 of a transistorselectionmatrix 10 is connected to the junction between the two base resistors120. When the signal line 12, connected to one of the current switches106, is selected, each of the base electrodes 122 of the transistors 112and 114 is established at approximately the voltage slightly below avalue of +E as explained in connection with the switching network 10 ofFIG. 1. .Each of the transistors 112 and 114, therefore, are biased inthe forward direction and are in a conductive condition. A negativecurrent pulse applied to the first primary winding 108 then flowsthrough the transformer winding 108 and the collector-to-emitter path ofthe transistor 1'12 and then the source E4 to ground. The current fiowin the primary Winding 108 induces a current in the direction of thearrow 124 in the connected memory line 94 or 96. A negative currentpulse supplied to the other primary winding 109 flows through thecollector to the emitter path of the transistor 112, and then throughthe source E4 to ground. Current how in the winding 109 induces acurrent in a direction opposite that of the arrow 124 in the connectedmemory line 94 or 96. Thus, by selecting one current switch in the rowswitch 98 and the column switch 100, information may be read from andwritten into any desired one of the memory cores of the memory matrix92.

Another form of a suitable current switch for the row and columnswitches 98 and 100 is that of the switch of FIG. 4. The current switch130 is similar to that of the current switch 106 of FIG. 3 with theexception that the connection of the two transistors 112 and 114 ischanged. Here the two emitter electrodes 118 are respectively connectedto the two primary windings 108 and 109 of the transformer 107, and eachof the collector electrodes 116 is,connected to the common'ground. Thebase electrodes 122 are directly connected to one of the signal lines 12of a transistor selection matrix. A base resistor 126 has one terminalconnected to a junction point between the signal line 12 and the baseelectrodes 122 of the transistors 112 and 114; the other terminal of thebase resistor 126 is connected to the positive terminal 138 of a biassource E5. The negative terminal 139 of the source E5 is connected tothe common ground. When a current switch arranged as the current switch.130 is used, the bias source E2 of the switching network 10 (FIG. 1) isomitted, and the emitter electrodes 52 of the transistors 44 and 45 ofthe first group are connected directly to ground. In such case, when thesignal line 12, connected to the current switch 130 (FIG. 4), isselected,

the base electrodes 122 of the PNP transistors 112 and 114 assume a biasof a value determined by the voltage drop across the base resistor 136,and the transistors 112 and 114 are placed in a conductive condition.Separate currents supplied to the primary windings 108 and 109 then flowthrough the emitter-to-collector paths of the transistors 112 and 114 tothe common ground. The current flows in the primary windings 108 and 109then induce opposite-polarity currents in the connected memory.line. Ifdesired, a separate emitter-follower amplifier can be connected betweeneach of the signal lines 12 of a selection'rnatrix, and a currentswitch, such as the current switches 106 and 13%, in order to furnish anadditional stage of current amplification.

A transistor switching network 140 adapted to commutate time-varyinginput signals is shown in FIG. 5. The switching network 141 is similarto that of FIG. 1 except that the bias source E2 is omitted and theemitter electrodes 52 of the transistors 44 and 45 of the first groupare connected to a matrix input terminal 142. Linear transformer 143 hasone terminal of its secondary winding 144 connected to the matrixterminal 142 and its other terminal connected to ground. Thetime-varying input signals are applied across the terminals of theprimary winding 145 of the transformer 142. The switching network 140has sixteen different output channels 147. The separate output channelsare connected to the separate signal lines 12. All the output channels147 are connected through separate series resistances 149 to thenegative terminal 150 of a bias source E6; the positive terminal 152 ofthe bias source is connected to ground. When an input signal is appliedto the primary winding 145 of the linear transformer 143, acorresponding voltage appears across the one resistor 149 connected tothe selected signal line 12 of the switching network 140. The dropacross the one resistor 149 is applied to the connected output channel147. Thus, the input signals can be commutated successively to desiredones of the output channels 147 by successively selecting signal lines12 in the manner described for the switching network of FIG. 1.

There has been described herein an improved transistor switching networkwherein a described one of a plurality of signal lines can be selectedin accordance with selection signals arranged in a combinatorial code.Networks according to the present invention are advantageous in that, inselecting the output line, the transistors provide a low-resistance pathto applied signals and also operate to amplify the selection signals.

What is claimed is:

1. In combination:

a coordinate array of transistors, of given conductivity type, arrangedin columns and rows;

I means providing a plurality of input signals;

' source means providing two operating voltages of different value;

a row selection array of transistors of one conductivity type connectedto receive the operating voltage of one of saidyalues for applying avoltage to the base electrodes of one row of the transistors in thecoordinate array in response to a particular combination of said inputsignals applied to the transistors of the row selection array; and

a column selection array of transistors of opposite conductivity type ofthe transistors of the row selection array connected to receive theoperating voltage of said other value for applying a voltage to theemitter electrodes of one column of the transistors in the coordinatearray in response to a particular combination of said input signalsapplied to the transistors of the column selection array, which voltageis in 'the forward direction relative the voltage ap plied to the baseelectrode of the transistor in the coordinate array which is common tothe row and column thereof selected by the row and column arrays, forplacing said transistor in condition to conduct.

2. A first and second group of elements as set forth in claim 1;

a plurality of loads; and 7 two sets of switch means, one set coupledbetween one coordinate array of transistors and the loads and the otherset coupled between the other coordinate array of transistors and theloads, each switch means in a set comprising a pair of normally openswitches, one for supplying acurrent in one direction to its load andthe other for supplying a current in the opposite direction to its load,each pair of switches, when actuated by a selected transistor in acoordinate array, being placed in condition to be closed, and furtherincluding means coupled to said pairs of switches for closing, in eachset of switch means, one switch in an actuated pair of switches andmaintaining the other switch open, whereby current flows through theclosed switch in one switch means in a given direction to its load, andthrough the closed switch in the other switch means in a given directionto its load.

3. The combination set forth in claim 2, wherein each pair of switchescomprises a pair of transistors normally in a cutoff condition, theselected transistor in a coordinate array applying a forward bias to aselected pair of said transistors placing them both in condition toconduct, and further including means coupled to the emitterto-collectorpaths of said transistors for causing current to flow through onetransistor of said selected pair of transistors.

4. In combination:

a coordinate array of transistors arranged in columns I sistors in thecoordinate array in response to a particular combination of said inputsignals applied to the transistors of the row selection array; and

a column selection array of NPN transistors connected to receive therelatively negative one of said operating voltages and coupled toanother electrode of the transistors of the coordinate array forapplying a relatively negative voltage to said other electrode in onecolumn of the transistors in the coordinate ar ray in response to aparticular combination of said input signals applied to the transistorsof the column selection array; and

one of said two electrodes comprising a base electrode and the other anemitter electrode, and said two voltages being applied by said twoselection arrays in a sense to forward bias the transistor in thecoordinate array which is common to the row and column thereof selectedby said selection arrays.

5. A switching network comprising:

an array of transistors arranged in columns and rows in a coordinatearray;

first and second pyramid arrays of other transistors, each transistorhaving a collector, an emitter and a base electrode, the transistors ofsaid coordinate array and of one of said pyramid arrays being of oneconductivity type and the transistors of said second pyramid array beingof the opposite conductivity type; and each such pyramid array having agroup of output transistors, in one case equal to the num ber of rows inthe coordinate array and in the other case equal to the number ofcolumns in the coordinate array;

operating voltage source means coupled to the transsistors of the firstand second pyramid arrays for supplying an operating voltage of onevalue in the forward direction to the transistors of the first pyramidarray and an operating voltage of a different value in the forwarddirection to the transistors of the other pyramid array;

means connecting the collector electrodes of the output transistors ofsaid first pyramid array to the base electrodes of the respective rowsof transistors in said coordinate array;

means connecting the collector electrodes of the output transistors ofsaid second pyramid array to the emitter electrodes of the respectivecolumn of transistors in said coordinate array;

a source of input signals; and

means for applying separate ones of said input signals to thetransistors of said first and second pyramid arrays, each said pyramidarray having a selected output in response to a particular combinationof said input signals applied to that pyramid array, said selectedoutputs of said first and second pyramid arrays jointly operating toplace a bias in the forward direction between the base and emitterelectrodes of one transistor in said coordinate array.

6. A switching array comprising: a

a plurality of loads;

a plurality of coupling means connected respectively to said loads;

a first plurality of drive lines'coupled respectively to each of saidloads; I

a second plurality of drive lines coupled respectively a to each of saidloads;

a first array of switching transistors, including a source of operatingcurrent, coupled to said first plurality of drive lines;

a second array of switching transistors, including a source of operatingcurrent, coupled to said second plurality'of drive lines;

l I each coupling means comprising a pair of further transistorelements; and

further control means coupled to said further transistor elements forcontrolling the conductivity of individual transistors of two selectedpairs thereof thereby to determine the directions of current flowthrough two selected loads.

References Cited by the Examiner UNITED STATES PATENTS 2,627,039 1/1953MacWilliams 340166 2,913,704 11/1959 Huang 340166 2,960,681 11/1960 Bonn340-l66 2,973,437 2/1961 Bradley et a1. 340-466 2,992,409 7/1961Lawrence 340166 NEIL c. READ, Primary Examiner.

25 A. I. KASPER, Assistant Examiner.

1. IN COMBINATION: A COORDINATE ARRAY OF TRANSISTORS, OF GIVENCONDUCTIVITY TYPE, ARRANGED IN COLUMNS AND ROWS; MEANS PROVIDING APLURALITY OF INPUT SIGNALS; SOURCE MEANS PROVIDING TWO OPERATINGVOLTAGES OF DIFFERENT VALUE; A ROW SELECTION ARRAY OF TRANSISTORS OF ONECONDUCTIVITY TYPE CONNECTED TO RECEIVE THE OPERATING VOLTAGE OF ONE OFSAID VALUES FOR APPLYING A VOLTAGE TO THE BASE ELECTRODES OF ONE ROW OFTHE TRANSISTORS IN THE COORDINATE ARRAY IN RESPONSE TO A PARTICULARCOMBINATION OF SAID INPUT SIGNALS APPLIED TO THE TRANSISTORS OF THE ROWSELECTION ARRAY; AND A COLUMN SELECTION ARRAY OF TRANSISTORS OF OPPOSITECONDUCTIVITY TYPE OF THE TRANSISTORS OF THE ROW SELECTION ARRAYCONNECTED TO RECEIVE THE OPERATING VOLTAGE OF SAID OTHER VALUE FORAPPLYING A VOLTAGE TO THE EMITTER ELECTRODES OF ONE COLUMN OF THETRANSISTORS IN THE COORDINATE ARRAY IN RESPONSE TO A PARTICULARCOMBINATION OF SAID INPUT SIGNALS APPLIED TO THE TRANSISTORS OF THECOLUMN SELECTION ARRAY, WHICH VOLTAGE IS IN THE FORWARD DIRECTIONRELATIVE THE VOLTAGE APPLIED TO THE BASE ELECTRODE OF THE TRANSISTOR INTHE COORDINATE ARRAY WHICH IS COMMON TO THE ROW AND COLUMN THEREOFSELECTED BY THE ROW AND COLUMN ARRAYS, FOR PLACING SAID TRANSISTOR INCONDITION TO CONDUCT.